A hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. It is a textual description consisting of expressions, statements and control structures. It is a language that describes hardware.

There are two major hardware description languages: VHDL and Verilog. There are different types of description in them: "dataflow, behavioral and structural". Example of dataflow of VHDL:

LIBRARY IEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTTIY NOT1 IS

PORT(

a : IN STD_LOGIC;

b : OUT STD_LOGIC;

END NOT1;

ARCHTECTURE behavioral OF not1 IS

BEGIN

b <= NOT1 a ;

END behavioral ;

👉VHDL stands for very high-speed integrated circuit Hardware Description Language. It is a programming language used to model a digital system by dataflow, behavioral and structural style of modeling.

👉VHDL Program Format:

The various sections used in VHDL program are shown in figure below. These sections are,

LIBRARY declaration which contains the list of libraries used in the program.

e.g. : ieee, std, work, etc.

The packages required in the program are,

1) ieee.std_logic_1164 (from the ieee library),
2) standard (from the std library) and
3) work (work library).

The declarations of the libraries are as follows,

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY std;

USE std.standard.all;

LIBRARY work;

USE work.all;

Since the libraries std and work are by default libraries, these libraries are need not to be declared. In the program the ieee library must be declared along with the STD_LOGIC (or STD_ULOGIC) data type used in the design.

2) ENTITY which declares the I/O pins of the circuit and

3) ARCHITECTURE which describes the detailed logical design aspects of the IC.

👉Describing a Design:

In VHDL an entity is used to describe a hardware module. An entity can be described using,

⦁ Entity declaration

⦁ Architecture

⦁ Configuration

⦁ Package declaration

⦁ Package body

👉Entity Declaration

It defines the names, input output signals and modes of a hardware module.

Syntax −

entity entity_name is

port decaratiin;

end entity_name;

An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will be input, output or inout..

👉Architecture −

Architecture can be described using structural, dataflow, behavioral or mixed style.

Syntax −

architecture architecture_name of entity_name

architecture_declarative_part;

begin

Statements;

end architecture_name;

Here, we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative part may contain variables, constants, or component declaration.

What is Data Flow Modeling?

In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.

Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct code.

Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.

In concurrent code, the following can be used −

⦁ Operators

⦁ The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);

⦁ The GENERATE statement;

⦁ The BLOCK statement

👉Behavioral Modeling

In this modeling style, the behavior of an entity as set of statements is executed sequentially in the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential.

PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially.

However, as a whole, any of these blocks is still concurrent with any other statements placed outside it.

One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it, we can build sequential circuits as well as combinational circuits.

The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and they are supposed to be used in sequential code only. VARIABLE can never be global, so its value cannot be passed out directly.

👉Structural Modeling

In this modeling, an entity is described as a set of interconnected components. The order of these statements is not important. The structural style of modeling describes only an interconnection of components without implying any behavior of the components themselves nor of the entity that they collectively represent.

In Structural modeling, architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin).

👉Logic Operation – AND GATE

VHDL Code:

Library ieee;

use ieee.std_logic_1164.all;

entity and1 is

port(x,y:in bit ; z:out bit);

end and1;

architecture sp of and1 is

begin

z<=x and y;

end sp;

👉Data Objects :

A data objects hold a value of specified type, which is created by means of an object declaration. In the following example signal is one of the type of data object. e.g. signal sl: std- logic

Type of data objects:

(i) Constant

(ii) File

(iii) Variable

(iv) Signals

1) Constant :

A constant is an object whose value may never be changed during the simulation process. The constant declaration contains one or more identifiers. The Syntax of constant is,

constant constant_name : type := value;

Example:

constant width: integer:= 8;

constant x: std_logic:= 16;

constant delay: time:= 10ns;

2) File :

A sequence of value called file. The value can be read or write to file using read procedures and write procedures respectively. The Syntax of file is:

file identifier : subtype_indication [ file_open_information ];

Example :

type IntegerFile is file of INTEGER;

file F1: IntegerFile;

3) Variables :

A variable is an object with single current value. A signal value of given type having different values assigned to different times called as variable. The Syntax of variable is,:

variable variable_name : type;

variable variable_name : type := initial_value;

Example :

variable A,B: bit;

variable sum : std_logic_vector(7 downto 0);

4) Signal :

Signal is an object with a past history of values. The term signal refers to objects declared by signal declarations and port declarations.

The Syntax of signal is :

signal signal_name : type;

signal signal_name : type := initial_value;

Example 1 :

signal A,B: std_logic;

signal DELAY: time:=10ns;

Example 2 :

entity testing is

port (A,B: in Std_Logic;

C: out Std_logic);

end entity;

architecture Ex_testing of testing is

signal Temp : Std_Logic;

begin

Temp<= A xor B;

C<= not Temp;

end architecture Ex_testing;

Each statement of the architecture Ex_testing may use any of the four signals: A, B, C declared as a port in the entity part (above the architecture section), Temp which is a single signal of the type Std_Logic

Data types are just attributes attached to the data that helps the VHDL compiler in understanding how to treat that particular data.